1. Field of the Invention
The present invention relates to a NAND type flash memory using, for example, EEPROM, and in particular, to a semiconductor memory device that enables multivalue data to be stored in a single cell.
2. Description of the Related Art
A NAND type flash memory has a plurality of memory cells arranged in a column direction and connected together in series to constitute NAND cells each of which is connected to a corresponding bit line via a select gate. Each bit line is connected to a latch circuit that latches write data and read data. All or half of the plurality of cells arranged in a row direction are simultaneously selected. A write operation or a read operation is executed on the simultaneously selected all or half of the cells at a time. A plurality of NAND cells arranged in the row direction constitute a block. An erase operation is executed on each block. The erase operation sets the threshold voltage of memory cells negative. The write operation injects electrons into memory cells to set the threshold voltage positive (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
In a NAND cell, the plurality of memory cells are connected together in series. Thus, during a read operation, unselected cells need to be on, so that a voltage (Vread) higher than the threshold voltage is applied to gate electrodes of the unselected cells. Thus, during the write operation, the threshold voltage set for the cells must not exceed Vread. Accordingly, during a write sequence, a program operation and a program verify read operation are repeatedly executed on each bit to control a threshold distribution so that the threshold voltage does not exceed Vread.
With the recently increased capacities of memories, multivalue memories have been developed which store at least 2 bits in a single cell. For example, storing 2 bits in a single cell requires four threshold distributions to be set so that the threshold voltages do not exceed Vread. The threshold distributions thus need to be controlled so that they are narrower than in the case where 1 bit and two threshold distributions are stored in a single cell. Further, storing 3 or 4 bits in a single cell requires 8 or 16 threshold distributions to be set. This in turn requires the distribution width of a single threshold voltage to be drastically reduced. Such a small threshold voltage distribution width requires the precise repetition of a program operation and a verify operation, disadvantageously reducing a write speed. Therefore, a semiconductor memory device has been desired which enables the write speed to be increased.